The present invention relates to the reduction of power consumption in digital circuits that rely upon a resistive load design such as pseudo NMOS and/or pseudo PMOS.
Reducing power consumption in digital circuits has become increasingly important, especially for real time clocking (RTC) applications which are operated by a low capacity battery (typically 200 mA-hr). For these applications, having low power consuming circuit elements may be essential to prolong battery lifetime.
Power consumption determines how much heat the circuit dissipates and how much energy is consumed. It can be decomposed into two components: static and dynamic. The dynamic component only occurs during transients, i.e. when the circuit is switching. It is due to the charging of capacitive elements and temporary current paths between the supply rails, and is, therefore, proportional to the switching frequency and duration: the greater the number of switching events and the longer they occur, the greater the dynamic power consumption. The static component on the other hand is present even when no switching occurs and is caused by static conductive paths between the supply rails or by leakage currents.
A bistable pulse generator, known as the Schmidt Trigger, is frequently used in RTC applications to xe2x80x9cclean upxe2x80x9d noisy signals by switching at a different threshold on rising and falling edges of an input signal. FIG. 1a is a transistor level diagram of a conventional Schmidt Trigger circuit. This type of circuit may consume a large current during switching transitions, i.e. a high dynamic power consumption. As FIG. 1b illustrates, intermediate transistors MP3 and MN3 provide a direct current path from the power source to ground during the transition phase. As a result, the dynamic power consumption of the Schmidt Trigger may be quite significant.
FIG. 2a shows the voltage characteristic of Schmidt Trigger circuit 1000 during a high to low transition. FIG. 2b demonstrates the current consumption of Schmidt Trigger circuit 1000 during this same period.
FIG. 2a shows input voltage v(in) decreasing linearly while output voltage v(out) remains constant at a high potential (xcx9c1.5 v) until input voltage v(in) reaches a particular threshold level (xcx9c0.3 v) whereupon output voltage v(out) drops suddenly and sharply (xcx9c0.0 v). Corresponding to the transition from a high to low voltage level, a significant current i(mp3) flows via intermediate transistor MP3 as indicated in FIG. 2b. 
FIG. 3a shows the voltage characteristic of Schmidt Trigger circuit 1000 during a low to high transition. FIG. 3b demonstrates the current consumption of Schmidt Trigger circuit 1000 during this same period
FIG. 3a shows input voltage v(in) increasing linearly while output voltage v(out) remains constant at a low potential (xcx9c0.0 v) until input voltage v(in) reaches a particular threshold level (xcx9c1.1 v) whereupon output voltage v(out) rises suddenly and sharply (xcx9c1.5 v). Corresponding to the transition from a low to high voltage level, a significant current i(mn3) flows via intermediate transistor MN3 as indicated in FIG. 3b. 
FIG. 4a shows a block diagram of a Current Mode Dual Trip Point design (a.k.a the Intel 82801BA circuit or I/O Controller Hub2 or South Bridge) for reducing dynamic power dissipation in a bistable pulse generator circuit. Current Mode circuit 4000 includes bias circuit 4900, low trip point inverter 4100, high trip point inverter 4200, tri-state inverter 4300, weak intermediate inverter 4400, and 2-stage output buffer 4500. Low trip inverter 4100 includes load network 4101 coupled to bias circuit 4900 and logic network 4102 coupled to input IN. High trip point inverter 4200 includes load network 4201 coupled to the bias circuit 4900 and logic network 4202 coupled to input IN.
FIG. 4b shows a transistor level diagram of the Current Mode Dual Trip Point design. In particular, the circuit shown in FIG. 4b uses pseudo N-MOS arranged circuitry (transistors MPP1, MPP2, MNP1, MNP2) to control the current during a low phase operation and pseudo P-MOS arranged circuitry (transistors MPN1, MNN1, MNN2) to control the current during a high phase operation. In particular, transistor MPP1 serves as a load network and transistors MPP2, MNP1, MNP2 serve as a logic network. Transistor MPN1 serves as a load network and transistors MNN1, MNN2 serve as a logic network.
The pseudo N-MOS arranged circuitry acts as a low trip point buffer 4100 changing its output voltage level at particular low input voltage level while the pseudo P-MOS arranged circuitry acts as a high trip point buffer 4200 changing its output voltage level at a particular low input voltage level. Dynamic power dissipation is reduced because load network resistance may be controlled. However, with this design there is unwanted static power dissipation due to the presence of bias circuit 4900 which consumes static current, as well as pseudo NMOS/PMOS arranged circuitry of high trip point inverter 4200 and pseudo PMOS arranged circuitry of low trip point inverter 4100.
FIG. 5a shows the voltage characteristic of Current Mode circuit 4000 during a high to low transition. FIG. 5b demonstrates the current consumption of Current Mode circuit 4000 during this same period.
FIG. 5a shows input voltage v(in) decreasing linearly while output voltage v(out) remains constant at a high potential (xcx9c1.5 v) until input voltage v(in) reaches a particular threshold level (xcx9c0.4 v) whereupon output voltage v(out) drops suddenly and sharply (xcx9c0.0 v).
FIG. 5b demonstrates that overall current consumption i(vss) during the high to low transition is reduced as compared with Schmidt Trigger circuit 1000. However, this overall current consumption i(vss) exists regardless of whether circuit 4000 is in the high to low transition state or merely in the steady state. Such steady state current is consumed by bias circuitry 4900 represented by currents i(mnb1) and i(mnb2), pseudo NMOS circuitry 4100 represented by current i(mnn2), and pseudo PMOS circuitry 4200 represented by current i(mnp2).
FIG. 6a shows input voltage v(in) increasing linearly while output voltage v(out) remains constant at a low potential (xcx9c0.0 v) until the input voltage v(in) reaches a particular threshold level (xcx9c0.9 v) whereupon output voltage v(out) rises suddenly and sharply (xcx9c1.5 v). FIG. 6b demonstrates that overall current consumption i(vss) during the low to high transition is reduced as compared with Schmidt Trigger circuit 1000. However, this overall current consumption i(vss) exists regardless of whether circuit 4000 is in the low to high transition state or merely in the steady state. Such steady state current is consumed by bias circuitry 4900 by currents i(mnb1) and i(mnb2), pseudo NMOS circuitry 4100 represented by current i(mnn2), and pseudo PMOS circuitry 4200 represented by current i(mnp2).